Intelligent Enterprise

5. Parallel or Bust: Computing at a Crossroads. When Intel announced it had canceled its successor to the Pentium 4 in 2004, the news marked a milestone in the history of computing. Rather than delivering on its promise of 10-GHz clock rates by the end of this decade, Intel joined AMD, IBM and Sun Microsystems in saying it could no longer build microprocessors with much higher clock rates.

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The media's mischaracterization of Moore's Law is now evident. Gordon Moore predicted the regular doubling of the number of transistors on a chip. The job of computer architects was to turn twice as many transistors into twice as much performance. Between 1986 and 2002 architects succeeded, and we saw the greatest sustained increase in performance in computing history. The problem was that they kept increasing the power dissipated per chip, and in 2004 it was obvious that the industry had hit a power wall. Today, microprocessors are about a factor of three slower than if we could keep increasing power and doubling performance every 18 months (see "Microprocessors Hit the Wall," right). Thus, while Moore's Law continues, power dissipation hit the wall.

Fortunately, parallel is more power-efficient. Power is a function of the square of the voltage, so if you double the number of processors but lower the clock rate and voltage some, you can increase the potential performance significantly without increasing power.

Hence, all microprocessor companies have been forced to bet their futures on multiple processors or "cores" per chip. Conservative companies like AMD and Intel sell just two cores per chip, while the radical companies like Sun offer eight cores per chip. To give a new media version of Moore's Law, it is likely that the number of cores per chip will double every 18 months.

This milestone means that we have reached the end of the "La-Z-Boy" programming era, where programmers could lounge about waiting for computer architects to double program performance every 18 months. Going forward, if programmers need speed improvements to, say, add new features, they are going to have to start writing parallel code that turns the potential performance of twice as many cores into delivered performance. Much of the future of enterprise applications and analytical systems will be told by how well programmers can take advantage of parallelism.

There's some confusion about terms now that we have passed this parallel crossroads. Multicore means multiple processors per chip. Some use the term socket instead of chip--the holder of the microprocessor package on the printed circuit board--because some companies are putting multiple chips into one package as their multicore product.

Another buzzword is multithreading. Since the programmer must create a thread per processor to keep processors busy, it sounds like the same idea. It is not. Multithreading is a trick architects use to try to keep a single processor busy. It does this by having extra copies of some hardware resources, like registers, but much less than another whole processor. Multithreaded processors switch to run another thread instead of waiting for, say, a cache miss. The Sun Niagara microprocessor, for example, has hardware support for four threads per processor. Although it appears to the programmer that the microprocessor is executing four times as many threads, it only executes one at a time. Hence, multithreading may improve performance per watt or performance per dollar, but it can't increase the peak performance of a microprocessor.

To add to the confusion, these terms are not mutually exclusive. The Sun Niagara uses both multi-core and multithreading. It has eight cores, each four-way multithreaded, presenting the programmer with the illusion of 32 threads executing simultaneously.

Companies are betting their futures on the success of parallel computing. The bet is not because of a research breakthrough that made parallel programming easy; it is because no hardware design can deliver faster single-program performance given the power wall. It is not clear that this bet will be successful; it has been tried many times over the decades and largely failed.

We need researchers and practitioners to address the biggest challenge and opportunity to face the IT industry in 50 years. If we solve the problem of making it easy to program thousands of processors efficiently, the future is rosy. If we don't, the IT industry will have to learn to live without the performance rush that it has been addicted to for decades.

David Patterson is co-author, with John L. Hennessy, of Computer Architecture: A Quantitative Approach (Fourth Edition), from which this article was adapted. He holds the Pardee Chair of Computer Science at the University of California, Berkeley, where has been teaching computer architecture since 1977. You can write to him at pattrsn@cs.berkeley.edu.